A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors
Journal of Electronic Testing: Theory and Applications
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide
MTV '04 Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
A statistical approach for full-chip gate-oxide reliability analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics
IBM Journal of Research and Development
Post-fabrication measurement-driven oxide breakdown reliability prediction and management
Proceedings of the 2009 International Conference on Computer-Aided Design
A Monte Carlo approach for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Gate oxide breakdown is an important reliability issue that has been widely studied at the individual transistor level, but has seen very little work at the circuit level. We first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to this phenomenon. The new approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 4.8-6.2× relaxation of the predicted lifetime with respect to the pessimistic area-scaling method for nominal process parameters. Next, we extend the failure analysis to include the effect of process variations, and derive that the circuit FP at a specified time instant has a lognormal distribution due to process variations. Circuits with variations show 19%-24% lifetime degradation against nominal analysis and 4.7-5.9× lifetime relaxation against area-scaling method under variations. Both parts of our work are verified by extensive simulations and proved to be effective, accurate and scalable.