Proceedings of the conference on Design, automation and test in Europe
A framework for accounting for process model uncertainty in statistical static timing analysis
Proceedings of the 44th annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Practical, fast Monte Carlo statistical static timing analysis: why and how
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variational capacitance extraction of on-chip interconnects based on continuous surface model
Proceedings of the 46th Annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Integration, the VLSI Journal
Placement optimization for yield improvement of switched-capacitor analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear statistical analysis for full-chip leakage power with spatial correlation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
Advanced variance reduction and sampling techniques for efficient statistical timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Robust spatial correlation extraction with limited sample via L1-norm penalty
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Hybrid modeling of non-stationary process variations
Proceedings of the 48th Design Automation Conference
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Process variation aware performance modeling and dynamic power management for multi-core systems
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 49th Annual Design Automation Conference
Dynamic clock stretching for variation compensation in VLSI circuit design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
Timing yield analysis considering process-induced temperature and supply voltage variations
Microelectronics Journal
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors
Proceedings of the Conference on Design, Automation and Test in Europe
Instruction-set extension under process variation and aging effects
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable methods for analyzing the circuit failure probability due to gate oxide breakdown
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Order statistics for correlated random variables and its application to at-speed testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The increased variability of process parameters makes it important yet challenging to extract the statistical characteristics and spatial correlation of process variation. Recent progress in statistical static-timing analysis also makes the extraction important for modern chip designs. Existing approaches extract either only a deterministic component of spatial variation or these approaches do not consider the actual difficulties in computing a valid spatial-correlation function, ignoring the fact that not every function and matrix can be used to describe the spatial correlation. Applying mathematical theories from random fields and convex analysis, we develop: 1) a robust technique to extract a valid spatial-correlation function by solving a constrained nonlinear optimization problem and 2) a robust technique to extract a valid spatial-correlation matrix by employing a modified alternative-projection algorithm. Our novel techniques guarantee to extract a valid spatial-correlation function and matrix from measurement data, even if those measurements are affected by unavoidable random noises. Experiment results, obtained from data generated by a Monte Carlo model, confirm the accuracy and robustness of our techniques and show that we are able to recover the correlation function and matrix with very high accuracy even in the presence of significant random noises