Stochastic finite elements: a spectral approach
Stochastic finite elements: a spectral approach
The Wiener--Askey Polynomial Chaos for Stochastic Differential Equations
SIAM Journal on Scientific Computing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
FastSies: a fast stochastic integral equation solver for modeling the rough surface effect
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
A divide-and-conquer algorithm for 3-D capacitance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variational capacitance extraction of on-chip interconnects based on continuous surface model
Proceedings of the 46th Annual Design Automation Conference
Robust simulation methodology for surface-roughness loss in interconnect and package modelings
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variational capacitance extraction and modeling based on orthogonal polynomial method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Hybrid modeling of non-stationary process variations
Proceedings of the 48th Design Automation Conference
Statistical extraction and modeling of inductance considering spatial correlation
Analog Integrated Circuits and Signal Processing
A dynamic method for efficient random mismatch characterization of standard cells
Proceedings of the International Conference on Computer-Aided Design
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An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient technique of Hermite polynomial collocation (HPC) is presented to extract the statistical capacitance. The capacitance covariances between windows are then calculated to reflect the spatial correlation. The proposed method is practical for chip-level extraction task, and the experiments on full-path extraction exhibit its high accuracy and efficiency.