Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Variational capacitance modeling using orthogonal polynomial method
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Stochastic integral equation solver for efficient variation-aware interconnect extraction
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Variational capacitance extraction of on-chip interconnects based on continuous surface model
Proceedings of the 46th Annual Design Automation Conference
Stochastic dominant singular vectors method for variation-aware extraction
Proceedings of the 47th Design Automation Conference
Rapid method to account for process variation in full-chip capacitance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, a new geometric variation model, referred to as the improved continuous surface variation (ICSV) model, is proposed to accurately imitate the random variation of on-chip interconnects. In addition, a new statistical capacitance solver is implemented to incorporate the ICSV model, the HPC [5] and weighted PFA [6] techniques. The solver also employs a parallel computing technique to greatly improve its efficiency. Experiments show that on a typical 65nm-technology structure, ICSV model has significant advantage over other existing models, and the new solver is at least 10X faster than the MC simulation with 10000 samples. The parallel solver achieves 7X further speedup on an 8-core machine. We conclude this paper with several criteria to discuss the trade-off between different geometric models and statistical methods for different scenarios.