Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM

Authors:
Jun-Fu Huang;Victor C. Y. Chang;Sally Liu;Kelvin Y. Y. Doong;Keh-Jeng Chang
Affiliations:
Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.;Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.;Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.;Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.;Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

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Abstract

For sub-9Onm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/SoC design yields significantly. This paper presents a recent silicon test chip experiment result which uses a set of innovative nanometer test structures and Monte-Carlo-based three-dimensional electromagnetic RC simulations to achieve silicon-correlated corner modeling of OCV that can be applied to the upcoming statistics-based timing analysis (SSTA) for design for manufacturability (DFM). Modeling and correlating OCV based on the randomly varying physical process parameters is therefore achieved for the realistic corner modeling of advanced copper and low-K.