Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
An algorithm for multiplication modulo (2/spl and/N-1)
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
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ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
Timing
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On the need for statistical timing analysis
Proceedings of the 42nd annual Design Automation Conference
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Design for Manufacturability and Statistical Design: A Comprehensive Approach
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Process-Variation Statistical Modeling for VLSI Timing Analysis
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Practical, fast Monte Carlo statistical static timing analysis: why and how
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On efficient Monte Carlo-based statistical static timing analysis of digital circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimization strategies to improve statistical timing
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
On the design of modulo 2n+1 dot product and generalized multiply-add units
Computers and Electrical Engineering
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding
Integration, the VLSI Journal
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This paper investigates the residue arithmetic as a solution for the design of variation-tolerant circuits. Motivated by the modular organization of residue processors, we comparatively study the sensitivity of residue arithmetic-based and binary processors to delay variations, and in particular the impact of delay variations onto the maximum critical path. Experiments are performed on two multiply-add (MAC) circuits based on residue and binary arithmetic. Results reveal that residue arithmetic-based circuits are up to 94% less sensitive to delay variation than binary circuits, thus leading to increased timing yield.