High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
High-Speed and Reduced-Area Modular Adder Structures for RNS
IEEE Transactions on Computers
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Modified Booth Modulo 2^n-1 Multipliers
IEEE Transactions on Computers
A Unified Design Space for Regular Parallel Prefix Adders
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
New Models of Prefix Adder Topologies
Journal of VLSI Signal Processing Systems
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
An efficient architecture for designing reverse converters based on a general three-moduli set
Journal of Systems Architecture: the EUROMICRO Journal
Modular array structure for non-restoring square root circuit
Journal of Systems Architecture: the EUROMICRO Journal
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Improved area-efficient weighted modulo 2n+ 1 adder design with simple correction schemes
IEEE Transactions on Circuits and Systems II: Express Briefs
Residue arithmetic for designing low-power multiply-add units
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Linear approximations of addition modulo 2n-1
FSE'11 Proceedings of the 18th international conference on Fast software encryption
Hierarchical residue number systems with small moduli and simple converters
International Journal of Applied Mathematics and Computer Science - Semantic Knowledge Engineering
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A randomized numerical aligner (rNA)
LATA'10 Proceedings of the 4th international conference on Language and Automata Theory and Applications
A Reconfigurable Channel Filter for Software Defined Radio Using RNS
Journal of Signal Processing Systems
Area-time efficient multi-modulus adders and their applications
Microprocessors & Microsystems
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
A randomized Numerical Aligner (rNA)
Journal of Computer and System Sciences
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
On the design of modulo 2n+1 dot product and generalized multiply-add units
Computers and Electrical Engineering
Efficient modulo 2n+1 multiplication for the idea block cipher
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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