An efficient tree architecture for modulo 2n + 1 multiplication
Journal of VLSI Signal Processing Systems - Special issue on VLSI arithmetic and implementations
A Simplified Architecture for Modulo (2n + 1) Multiplication
IEEE Transactions on Computers
Reducing power by optimizing the necessary precision/range of floating-point arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design of synchronous and asynchronous variable-latency pipelined multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS Logic Circuit Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
A Low Power High Performance Distributed DCT Architecture
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Minimization of switching activities of partial products for designing low-power multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Low-power circuits and technology for wireless digital systems
IBM Journal of Research and Development
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of a high-speed matrix multiplier based on word-width decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing CMOS Circuits for Low Power
Designing CMOS Circuits for Low Power
A power-driven multiplication instruction-set design method for ASIPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Wireless Communications
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
Proposed low power, high speed adder-based 65-nm Square root circuit
Microelectronics Journal
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
WSEAS Transactions on Circuits and Systems
An efficient EPI and energy consumption of 32 bit ALU using Shannon theorem based adder approach
WSEAS Transactions on Circuits and Systems
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In this paper, we have developed a new full-adder cell using multiplexing control input techniques (MCIT) for the sum operation and the Shannon-based technique to implement the carry. The proposed adder cell is applied to the design of several 8-bit array multipliers, namely a Braun array multiplier, a CSA multiplier, and Baugh-Wooley multipliers. The multiplier circuits are designed using DSCH2 VLSI CAD tools and their layouts are generated by Microwind 3 VLSI CAD tools. The output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulated results. We have also calculated energy per instruction (EPI), throughput, latency, signal-to-noise ratio (SNR), and the effect of temperature on the drain current by using the generated layout output parameter of a BSIM 4 advanced analyzer. The simulated results of the proposed adder-based multiplier circuit are compared with a cell multiplier that utilizes a MCIT-based adder, a cell multiplier composed of complementary pass transistor logic-based (CPL) adders and those of other published multipliers circuits. From the analysis of these simulated results, it was found that the proposed multiplier circuit gives better performance in terms of power, propagation delay, latency and throughput than other published results.