A Low Power High Performance Distributed DCT Architecture

Authors:
Archana Chidanandan
Affiliations:
-
Venue:
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Year:
2002

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Abstract

A new distributed arithmetic architecture, NEDA, is presented in this paper. NEDA is a low power optimized architecture based on the distributed arithmetic paradigm. In addition to low power performance, NEDA offers high speed and reduced area. In NEDA, inner product computational module has been proved, mathematically, to require only additions. Moreover, minimum number of additions is used by exploiting the redundancy in the adder array. Such properties have made a NEDA unit a basic computational module for high performance DSP architectures. A case study of 8 x 8 DCT NEDA-based architecture is analyzed. Savings exceeding 88% are achieved for the DCT implementation.