A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
DCT Implementation with Distributed Arithmetic
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A Low Power High Performance Distributed DCT Architecture
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A simple processor core design for DCT/IDCT
IEEE Transactions on Circuits and Systems for Video Technology
An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms
Proceedings of the 24th symposium on Integrated circuits and systems design
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
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Variable radix-2 multibit coding algorithm is presented and implemented in discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT). Variable radix-2 multibit coding means the 2k signed digit (SD) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. The VLSI architecture employing this algorithm shows superior performance for the parallel processing compared with the ROM-based distributed arithmetic architecture and ROM-based parallel multiplication. Since DCT/IDCT core needs matrix transposition, we propose an orthogonal transpose memory scheme that satisfies horizontal and vertical signal transfer. The simulation shows that the core is compatible with IEEE STD 1180-1990 and it runs at a rate of 400 Mpixels/s, which is up to 20 times as fast as design. The fabricated IDCT core runs at 54 MHz, features 28 latencies, consumes 0.9 W of power at 3.3 V and occupies 24 mm2 in 0.6 µm triple metal CMOS technology for HDTV video decoder.