A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Digital Computer Arithmetic
A technology independent MOS multiplier generator
DAC '84 Proceedings of the 21st Design Automation Conference
Integer Multiplication with Overflow Detection or Saturation
IEEE Transactions on Computers - Special issue on computer arithmetic
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder
Integration, the VLSI Journal
Minimal Weight Digit Set Conversions
IEEE Transactions on Computers
A new array architecture for signed multiplication using Gray encoded radix-2m operands
Integration, the VLSI Journal
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Reconfigurable custom floating-point instructions (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
High-speed and low-power PID structures for embedded applications
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A new high radix-2r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers
ACM SIGARCH Computer Architecture News
| Hi-index | 14.99 |
A multibit recoding algorithm for signed two's complement binary numbers is presented and proved. In general, a k+1-bit recoding will result in a signed-digit (SD) representation of the binary number in radix 2/sup k/, using digits -2/sup k-1/ to +2/sup k-1/ including 0. It is shown that a correct SD representation of the original number is obtained by scanning K+1-tuples (k驴1) with one bit overlapping between adjacent groups. Recording of binary numbers has been used in computer arithmetic with 3-bit recoding being the dominant scheme. With the emergence of very high speed adders, hardware parallel multipliers using multibit recoding with k