An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation

Authors:
Hak-soo Yu;Jacob A. Abraham
Affiliations:
Computer Engineering Research Center, The University of Texas at Austin, Austin, TX;Computer Engineering Research Center, The University of Texas at Austin, Austin, TX
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

In this paper, we present an efficient 3-bit-scan multiplier without overlapping bits which has good power-delay-area tradeoffs. Generation of partial product terms in this multiplier is performed in parallel with the multiplication operation. Parallel partial product generation results in a multiplier which is faster than conventional sequential multipliers. The architecture of the 3-bit-scan multiplier without overlapping bits is therefore suitable for synchronous sequential multipliers which are required to operate at low power and at relatively high speed for their area.