CMOS floating-point unit for the S/390 parallel enterprise server G4
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
High-Radix Design of a Scalable Modular Multiplier
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
The IBM eServer z990 floating-point unit
IBM Journal of Research and Development
New approach to design for reusability of arithmetic cores in systems-on-chip
Integration, the VLSI Journal
Efficient implementation of 3X for radix-8 encoding
Microelectronics Journal
The S/390 G5 floating-point unit
IBM Journal of Research and Development
A goldschmidt division method with faster than quadratic convergence
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
| Hi-index | 0.00 |
The multiplier of a S/390 CMOS microprocessor is described. It is implemented in an aggressive static CMOS technology with 0.20 \mum effective channel length. The multiplier has been demonstrated in a single-image shared-memory multiprocessor at frequencies up to 400 MHz. The multiplier requires three machine cycles for a total latency of 7.5 ns. Though, the design can support a latency of 4.0 ns if the latches are removed. The design goal was to implement a versatile S/390 multiplier with reasonable performance at a very aggressive cycle time. The multiplier implements a radix-8 Booth algorithm and is capable of supporting S/390 floating-point and fixed-point multiplications and also division and square root. Logic design and physical design issues are discussed relating to the Booth decode and counter tree implementations.