A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms

Authors:
David Guevorkian;Petri Liuha;Aki Launiainen;Konsta Punkka;Ville Lappalainen
Affiliations:
Nokia Research Center, Tampere, Finland;Nokia Research Center, Tampere, Finland;Nokia Research Center, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Nokia Multimedia Business Unit, Tampere, Finland
Venue:
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2005

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Abstract

In our previous work, general principles to develop efficient architectures for matrix-vector arithmetics and video/image processing were proposed based on high-radix (4,8, or 16) multiplier extensions. In this work, we propose a radix-8 multiplier design and its extension to Multifunctional Architecture for Video and Image Processing (MAVIP). MAVIP may operate either as a programmable unit with DSP-specific operations such as multiplication, multiply-accumulate, parallel addition or as one or another HWA such as matrix-vector multiplier, FIR filter, or sum-of-absolute-difference accelerator. Simulations indicate that being a small device, MAVIP has competitive performance in video coding.