Fast multiplication: algorithms and implementation
Fast multiplication: algorithms and implementation
Basic digit sets for radix representation
Journal of the ACM (JACM)
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
Integration, the VLSI Journal
Modified Booth Algorihtm for High Radix Multiplication
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Redundant Binary Booth Recoding
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Binary Multiplication Radix-32 and Radix-256
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
High-speed and low-power PID structures for embedded applications
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A new high radix-2r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers
ACM SIGARCH Computer Architecture News
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For progressively higher radices, the reduction in partial products obtained by the well-known modified Booth multiplier recoding is offset by the need to precompute a rapidly increasing store of odd multiples of the multiplicand as inputs to each partial product generator (PPG). We propose secondary radix multiplier recoding schemes reducing the number of odd multiples required in the store for very high radix recodings (e.g., radix 2^r for 5 \le r \le 16). The proposed recoding schemes allow reduction of the number of partial products in the implementation by factors between and beyond the reduction factors of 2, 3, and 4 that can be achieved by traditional Booth recodings to radices 4, 8, and 16, respectively. We develop the theory of these recodings and provide methodology for secondary radix selection. Finally, we summarize latency and cost evaluations of selected implementations indicating potential cost and performance/cost advantages for practical operand sizes.