Binary Multiplication Radix-32 and Radix-256
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Secondary Radix Recodings for Higher Radix Multipliers
IEEE Transactions on Computers
Modified booth multipliers with a regular partial product array
IEEE Transactions on Circuits and Systems II: Express Briefs
Multiplication acceleration through twin precision
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of power-efficient configurable booth multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
IEEE Transactions on Computers
Area-Efficient Multipliers Based on Multiple-Radix Representations
IEEE Transactions on Computers
High-speed and low-power PID structures for embedded applications
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
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This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size N of the operands. As a result, the critical path is drastically reduced to 33√ N / 2 -- 3 with no area overhead in comparison to modified Booth algorithm that shows a critical path of N/2 in adder stages. For instance, only 7 adder stages are needed for a 64-bit two's complement multiplier. Confronted to reference algorithms for N=64, important gain ratios of 1.62, 1.71, 2.64 are obtained in terms of multiply-time, energy consumption per multiplyoperation, and total gate count, respectively.