High-speed and low-power PID structures for embedded applications

Authors:
Abdelkrim K. Oudjida;Nicolas Chaillet;Ahmed Liacha;Mustapha Hamerlain;Mohamed L. Berrandjia
Affiliations:
Microelectronics and Nanotechnology Division, Centre de Développement des Technologies Avancées, Algiers, Algeria;AS2M Department, FEMTO-ST Institute, Besançon, France;Microelectronics and Nanotechnology Division, Centre de Développement des Technologies Avancées, Algiers, Algeria;Microelectronics and Nanotechnology Division, Centre de Développement des Technologies Avancées, Algiers, Algeria;Microelectronics and Nanotechnology Division, Centre de Développement des Technologies Avancées, Algiers, Algeria
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

In embedded control applications, control-rate and energy-consumption are two critical design issues. This paper presents a series of high-speed and lowpower finite-word-length PID controllers based on a new recursive multiplication algorithm. Compared to published results into the same conditions, savings of 431% and 20% are respectively obtained in terms of control-rate and dynamic power consumption. In addition, the new multiplication algorithm generates scalable PID structures that can be tailored to the desired performance and power budget. All PIDs are implemented at RTL level as technology-independent reusable IP-cores. They are reconfigurable according to two compile-time constants: set-point word-length and latency.