The IBM system/360 model 91: floating-point execution unit
IBM Journal of Research and Development
A Fast 1-D Serial-Parallel Systolic Multiplier
IEEE Transactions on Computers
FLIP-FLOP: a stack-oriented multiprocessing system
ACM SIGFORTH Newsletter - Special issue: Hardware
Multiplexer Based Reconfiguration for Virtex Multipliers
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
The Fastest Multiplier on FPGAs with Redundant Binary Representation
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Uniform Shift Multiplication Algorithms Without Overflow
IEEE Transactions on Computers
FPGA-based real-time remote monitoring system
Computers and Electronics in Agriculture
High-speed and low-power PID structures for embedded applications
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
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A simplified proof of a modification of Booth's multiplication algorithm by MacSorley to a form which examines three multiplier bits at a time is presented. In comparison with the original Booth's algorithm, which examines two bits at a time, the modified algorithm requires half the nutmber of iterations at the cost of somewhat increased complexity for each iteration.