Planning a computer system: Project Stretch
Planning a computer system: Project Stretch
On the Complexity of Table Lookup for Iterative Division
IEEE Transactions on Computers
Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal Verification of Parametric Multiplicative Division Implementations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Minimum Mean Running Time Function Generation Using Read-Only Memory
IEEE Transactions on Computers
On Optimal Ierative Schemes for High-Speed Division
IEEE Transactions on Computers
Pipeline Iterative Arithmetic Arrays
IEEE Transactions on Computers
Parallel Multiplicative Algorithms for Some Elementary Functions
IEEE Transactions on Computers
On-Line Algorithms for Division and Multiplication
IEEE Transactions on Computers
Design of High-Speed Digital Divider Units
IEEE Transactions on Computers
Effective Pipelining of Digital Systems
IEEE Transactions on Computers
On Division by Functional Iteration
IEEE Transactions on Computers
High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm
IEEE Transactions on Computers
A Proof of the Modified Booth's Algorithm for Multiplication
IEEE Transactions on Computers
On the Precision Attainable with Various Floating-Point Number Systems
IEEE Transactions on Computers
Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication
IEEE Transactions on Computers
Pipelining of Arithmetic Functions
IEEE Transactions on Computers
A Comparison of Some Theoretical Models of Parallel Computation
IEEE Transactions on Computers
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The principal requirement for the Model 91 floating-point execution unit was that it be designed to support the instructionissuing rate of the processor. The chosen solution was to develop separate, instruction-oriented algorithms for the add, multiply, and divide functions. Linked together by the floating-point instruction unit, the multiple execution units provide concurrent instruction execution at the burst rate of one instruction per cycle.