Communications of the ACM
On Optimal Ierative Schemes for High-Speed Division
IEEE Transactions on Computers
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
The IBM system/360 model 91: floating-point execution unit
IBM Journal of Research and Development
On the Complexity of Table Lookup for Iterative Division
IEEE Transactions on Computers
CMOS floating-point unit for the S/390 parallel enterprise server G4
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Formal Verification of Parametric Multiplicative Division Implementations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Minimum Mean Running Time Function Generation Using Read-Only Memory
IEEE Transactions on Computers
The Sign/Logarithm Number System
IEEE Transactions on Computers
The S/390 G5 floating-point unit
IBM Journal of Research and Development
Bit-Sequential Arithmetic for Parallel Processors
IEEE Transactions on Computers
Journal of Signal Processing Systems
The setup for triangle rasterization
EGGH'96 Proceedings of the Eleventh Eurographics conference on Graphics Hardware
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In order to avoid the time delays associated with linearly convergent division based on subtraction, other iterative schemes can be used. These are based on 1) series expansion of the reciprocal, 2) multiplicative sequence, or 3) additive sequence convergent to the quotient. These latter techniques are based on finding the root of an arbitrary function at either the quotient or reciprocal value. A Newton-Raphson iteration or root finding iteration can be used.