Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

Authors:
F. Javier López-Martínez;Eduardo Castillo-Sánchez;José Tomás Entrambasaguas;Eduardo Martos-Naya
Affiliations:
Departamento Ingeniería de Comunicaciones, Universidad de Málaga, Málaga, Spain 29071;Departamento Ingeniería de Comunicaciones, Universidad de Málaga, Málaga, Spain 29071;Departamento Ingeniería de Comunicaciones, Universidad de Málaga, Málaga, Spain 29071;Departamento Ingeniería de Comunicaciones, Universidad de Málaga, Málaga, Spain 29071
Venue:
Journal of Signal Processing Systems
Year:
2011

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Abstract

A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.