Evaluation of CORDIC Algorithms for FPGA Design

Authors:
Javier Valls;Martin Kuhlmann;Keshab K. Parhi
Affiliations:
Department of Ingenieria Electronica, Universidad Politecnica de Valencia, 46730 Grao de Gandia, Valencia, Spain;Broadcom Corporation, 16215 Alton Pkwy, Irvine, CA 92619, USA;Broadcom Corporation, 16215 Alton Pkwy, Irvine, CA 92619, USA
Venue:
Journal of VLSI Signal Processing Systems
Year:
2002

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Abstract

This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional two's complement architecture leads to the best performance.