IEEE Transactions on Pattern Analysis and Machine Intelligence
Authenticating Edges Produced by Zero-Crossing Algorithms
IEEE Transactions on Pattern Analysis and Machine Intelligence
Phase-based disparity measurement
CVGIP: Image Understanding
Performance of phase-based algorithms for disparity estimation
Machine Vision and Applications - Special issue on performance evaluation
A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
Stability of Phase Information
IEEE Transactions on Pattern Analysis and Machine Intelligence
Deformable Kernels for Early Vision
IEEE Transactions on Pattern Analysis and Machine Intelligence
Hierarchical Model-Based Motion Estimation
ECCV '92 Proceedings of the Second European Conference on Computer Vision
Phase Difference Stereo Disparity Computation on a SIMD Parallel Machine
HPCN Europe '97 Proceedings of the International Conference and Exhibition on High-Performance Computing and Networking
Advances in Computational Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
Fast Unambiguous Stereo Matching Using Reliability-Based Dynamic Programming
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Real-Time Large Disparity Range Stereo-System using FPGAs
ICVS '06 Proceedings of the Fourth IEEE International Conference on Computer Vision Systems
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm
Machine Vision and Applications
The Tyzx DeepSea G2 Vision System, ATaskable, Embedded Stereo Camera
CVPRW '06 Proceedings of the 2006 Conference on Computer Vision and Pattern Recognition Workshop
High-Quality Real-Time Stereo Using Adaptive Cost Aggregation and Dynamic Programming
3DPVT '06 Proceedings of the Third International Symposium on 3D Data Processing, Visualization, and Transmission (3DPVT'06)
Real-time Stereo Vision FPGA Chip with Low Error Rate
MUE '07 Proceedings of the 2007 International Conference on Multimedia and Ubiquitous Engineering
Low-Cost Stereo Vision on an FPGA
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A 12-Gb/s DEMUX Implemented with SiGe high-speed FPGA circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural modifications to enhance the floating-point performance of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved-Quality Real-Time Stereo Vision Processor
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
VLSI-efficient scheme and FPGA realization for robotic mapping in a dynamic environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A compact harmonic code for early vision based on anisotropic frequency channels
Computer Vision and Image Understanding
Improving FPGA performance for carry-save arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-port abstraction layer for FPGA intensive memory exploitation applications
Journal of Systems Architecture: the EUROMICRO Journal
Accurate hardware-based stereo vision
Computer Vision and Image Understanding
A real-time fuzzy hardware structure for disparity map computation
Journal of Real-Time Image Processing
IEEE Transactions on Intelligent Transportation Systems
Real-Time System for High-Image Resolution Disparity Estimation
IEEE Transactions on Image Processing
Real-Time Stereo Matching Using Orthogonal Reliability-Based Dynamic Programming
IEEE Transactions on Image Processing
Nonlinearities in Stereoscopic Phase-Differencing
IEEE Transactions on Image Processing
FPGA Design and Implementation of a Real-Time Stereo Vision System
IEEE Transactions on Circuits and Systems for Video Technology
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
On-chip semidense representation map for dense visual features driven by attention processes
Journal of Real-Time Image Processing
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In this work, we present a real-time implementation of a stereo algorithm on field-programmable gate array (FPGA). The approach is a phase-based model that allows computation with sub-pixel accuracy. The algorithm uses a robust multi-scale and multi-orientation method that optimizes the estimation extraction with respect to the local image structure support. With respect to the state of the art, our work increases the on-chip power of computation compared to previous approaches in order to obtain a good accuracy of results with a large disparity range. In addition, our approach is specially suited for unconstrained environments applications thanks to the robustness of the phase information, capable of dealing with severe illumination changes and with small affine deformation between the image pair. This work also includes the rectification images circuitry in order to exploit the epipolar constraints on the chip. The dedicated circuit can rectify and process images of VGA resolution at a frame rate of 57 fps. The implementation uses a fine pipelined method (also with superscalar units) and multiple user defined parameters that lead to a high working frequency and a good adaptability to different scenarios. In the paper, we present different results and we compare them with state of the art approaches.