Intensity- and Gradient-Based Stereo Matching Using Hierarchical Gaussian Basis Functions
IEEE Transactions on Pattern Analysis and Machine Intelligence
Digital Image Processing
A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
Non-parametric Local Transforms for Computing Visual Correspondence
ECCV '94 Proceedings of the Third European Conference-Volume II on Computer Vision - Volume II
Tyzx DeepSea High Speed Stereo Vision System
CVPRW '04 Proceedings of the 2004 Conference on Computer Vision and Pattern Recognition Workshop (CVPRW'04) Volume 3 - Volume 03
On the Computational Power of Winner-Take-All
Neural Computation
The Tyzx DeepSea G2 Vision System, ATaskable, Embedded Stereo Camera
CVPRW '06 Proceedings of the 2006 Conference on Computer Vision and Pattern Recognition Workshop
High-Quality Real-Time Stereo Using Adaptive Cost Aggregation and Dynamic Programming
3DPVT '06 Proceedings of the Third International Symposium on 3D Data Processing, Visualization, and Transmission (3DPVT'06)
Stereo for Image-Based Rendering using Image Over-Segmentation
International Journal of Computer Vision
International Journal of Computer Vision
Curious George: An attentive semantic robot
Robotics and Autonomous Systems
Little Ben: The Ben Franklin Racing Team's entry in the 2007 DARPA Urban Challenge
Journal of Field Robotics - Special Issue on the 2007 DARPA Urban Challenge, Part II
A Convex Formulation of Continuous Multi-label Problems
ECCV '08 Proceedings of the 10th European Conference on Computer Vision: Part III
An Optimized Software-Based Implementation of a Census-Based Stereo Matching Algorithm
ISVC '08 Proceedings of the 4th International Symposium on Advances in Visual Computing
Flexible hardware-based stereo matching
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Face detection with the modified census transform
FGR' 04 Proceedings of the Sixth IEEE international conference on Automatic face and gesture recognition
High-accuracy stereo depth maps using structured light
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
Comparison of nonparametric transformations and bit vector matching for stereo correlation
IWCIA'04 Proceedings of the 10th international conference on Combinatorial Image Analysis
Distortion compensation for movement detection based on dense optical flow
ISVC'11 Proceedings of the 7th international conference on Advances in visual computing - Volume Part I
Low-cost FPGA stereo vision system for real time disparity maps calculation
Microprocessors & Microsystems
Stereo matching using weighted dynamic programming on a single-direction four-connected tree
Computer Vision and Image Understanding
Hardware design considerations for edge-accelerated stereo correspondence algorithms
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm
Computer Vision and Image Understanding
A precise real-time stereo algorithm
Proceedings of the 27th Conference on Image and Vision Computing New Zealand
Real-time architecture for a robust multi-scale stereo engine on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-performance dense block matching solution for automotive 6D-vision
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Efficient and high performance FPGA-based rectification architecture for stereo vision
Microprocessors & Microsystems
Evaluation of stereo correspondence algorithms and their implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
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To enable both accurate and fast real-time stereo vision in embedded systems, we propose a novel stereo matching algorithm that is designed for high efficiency when realized in hardware. We evaluate its accuracy using the Middlebury Stereo Evaluation, revealing its high performance at minimum tolerance. To outline the resource efficiency of the algorithm, we present its realization as an Intellectual Property (IP) core that is designed for the deployment in Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs).