A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
Calculating Dense Disparity Maps from Color Stereo Images, an Efficient Implementation
International Journal of Computer Vision
Real-Time Correlation-Based Stereo Vision with Reduced Border Errors
International Journal of Computer Vision
Multiple Stereo Matching Using an Extended Architecture
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Advances in Computational Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
Real-Time Stereo by using Dynamic Programming
CVPRW '04 Proceedings of the 2004 Conference on Computer Vision and Pattern Recognition Workshop (CVPRW'04) Volume 3 - Volume 03
Adaptive Support-Weight Approach for Correspondence Search
IEEE Transactions on Pattern Analysis and Machine Intelligence
A versatile stereo implementation on commodity graphics hardware
Real-Time Imaging
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm
Machine Vision and Applications
Local Stereo Matching with Segmentation-based Outlier Rejection
CRV '06 Proceedings of the The 3rd Canadian Conference on Computer and Robot Vision
An Introduction to 3D Computer Vision Techniques and Algorithms
An Introduction to 3D Computer Vision Techniques and Algorithms
An evolvable hardware system in Xilinx Virtex II Pro FPGA
International Journal of Innovative Computing and Applications
A Real-Time Occlusion Aware Hardware Structure for Disparity Map Computation
ICIAP '09 Proceedings of the 15th International Conference on Image Analysis and Processing
Segmentation-based adaptive support for accurate stereo correspondence
PSIVT'07 Proceedings of the 2nd Pacific Rim conference on Advances in image and video technology
Distributed real-time stereo matching on smart cameras
Proceedings of the Fourth ACM/IEEE International Conference on Distributed Smart Cameras
Accurate hardware-based stereo vision
Computer Vision and Image Understanding
Real-time stereo vision on a reconfigurable system
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Real-Time System for High-Image Resolution Disparity Estimation
IEEE Transactions on Image Processing
FPGA Design and Implementation of a Real-Time Stereo Vision System
IEEE Transactions on Circuits and Systems for Video Technology
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight
IEEE Transactions on Circuits and Systems for Video Technology
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Stereo correspondence is a popular algorithm for the extraction of depth information from a pair of rectified 2D images. Hence, it has been used in many computer vision applications that require knowledge about depth. However, stereo correspondence is a computationally intensive algorithm and requires high-end hardware resources in order to achieve real-time processing speed in embedded computer vision systems. This paper presents an overview of the use of edge information as a means to accelerate hardware implementations of stereo correspondence algorithms. The presented approach restricts the stereo correspondence algorithm only to the edges of the input images rather than to all image points, thus resulting in a considerable reduction of the search space. The paper highlights the benefits of the edge-directed approach by applying it to two stereo correspondence algorithms: an SAD-based fixed-support algorithm and a more complex adaptive support weight algorithm. Furthermore, we present design considerations about the implementation of these algorithms on reconfigurable hardware and also discuss issues related to the memory structures needed, the amount of parallelism that can be exploited, the organization of the processing blocks, and so forth. The two architectures (fixed-support based versus adaptive-support weight based) are compared in terms of processing speed, disparity map accuracy, and hardware overheads, when both are implemented on a Virtex-5 FPGA platform.