Evolving hardware with genetic learning: a first step towards building a Darwin machine
Proceedings of the second international conference on From animals to animats 2 : simulation of adaptive behavior: simulation of adaptive behavior
Simulation of Evolable Hardware to Solve Low Level Image Processing Tasks
EvoIASP '99/EuroEcTel '99 Proceedings of the First European Workshops on Evolutionary Image Analysis, Signal Processing and Telecommunications
Image Filter Design with Evolvable Hardware
Proceedings of the Applications of Evolutionary Computing on EvoWorkshops 2002: EvoCOP, EvoIASP, EvoSTIM/EvoPLAN
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
Evolving an Adaptive Digital Filter
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers
EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
Evolvable Components: From Theory to Hardware Implementations
Evolvable Components: From Theory to Hardware Implementations
A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Image Processing, Analysis, and Machine Vision
Image Processing, Analysis, and Machine Vision
An implicit context representation for evolving image processing filters
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
An evolvable image filter: experimental evaluation of a complete hardware implementation in FPGA
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Explorations in design space: unconventional electronics designthrough artificial evolution
IEEE Transactions on Evolutionary Computation
Evolving oscillators in silico
IEEE Transactions on Evolutionary Computation
Evolutionary functional recovery in virtual reconfigurable circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hardware accelerators for Cartesian genetic programming
EuroGP'08 Proceedings of the 11th European conference on Genetic programming
A method for design of impulse bursts noise filters optimized for FPGA implementations
Proceedings of the Conference on Design, Automation and Test in Europe
Evolutionary approach to improve wavelet transforms for image compression in embedded systems
EURASIP Journal on Advances in Signal Processing - Special issue on biologically inspired signal processing: analyses, algorithms and applications
Proceedings of the 13th annual conference companion on Genetic and evolutionary computation
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling
Microprocessors & Microsystems
Hardware design considerations for edge-accelerated stereo correspondence algorithms
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
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In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution by Martinek and Sekanina, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 sec in average.