An evolvable hardware system in Xilinx Virtex II Pro FPGA
International Journal of Innovative Computing and Applications
A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Intrinsic evolution of digital circuits using evolutionary algorithms
Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Analysis of reconfigurable logic blocks for evolvable digital architectures
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Improving flexibility in on-line evolvable systems by reconfigurable computing
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Genetic Algorithm for Boolean minimization in an FPGA cluster
The Journal of Supercomputing
Evolvable hardware design based on a novel simulated annealing in an embedded system
Concurrency and Computation: Practice & Experience
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling
Microprocessors & Microsystems
On the Evolution of Hardware Circuits via Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Randomly connecting networks have proven to be universal computing machines. By interconnecting a set of nodes in a random way one can model very complicated non-linear dynamic systems. Although random Boolean networks (RBN) use Boolean functions as their basic component, there are not hardware implementations of such systems. The absence of implementations is mainly due to the arbitrary connectionism exhibited by the network, and connection flexibility use to be very expensive in terms of hardware resources. In this paper we present an onchip self-reconfigurable approach for providing a flexible connectionism at very low resource cost by partially reconfiguring Virtex II FPGAs.