Evolving hardware with genetic learning: a first step towards building a Darwin machine
Proceedings of the second international conference on From animals to animats 2 : simulation of adaptive behavior: simulation of adaptive behavior
Migration Policies, Selection Pressure, and Parallel Evolutionary Algorithms
Journal of Heuristics
Ant Colony System for the Design of Combinational Logic Circuits
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
A Genetic Programming Approach to Logic Function Synthesis by Means of Multiplexers
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Representations for Genetic and Evolutionary Algorithms
Representations for Genetic and Evolutionary Algorithms
Adaptive immune genetic algorithm for logic circuit design
Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation
Hardware accelerators for Cartesian genetic programming
EuroGP'08 Proceedings of the 11th European conference on Genetic programming
Parallel genetic algorithms on programmable graphics hardware
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
Evolving hardware by dynamically reconfiguring xilinx FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
POEtic: a prototyping platform for bio-inspired hardware
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Genetic Programming and Evolvable Machines
Parallel algorithm for evolvable-based boolean synthesis on GPUs
Analog Integrated Circuits and Signal Processing
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Evolutionary algorithms are an alternative option to the Boolean synthesis due to that they allow one to create hardware structures that would not be able to be obtained with other techniques. This paper shows a parallel genetic programming (PGP) Boolean synthesis implementation based on a cluster of FPGAs that takes full advantage of parallel programming and hardware/software co-design techniques. The performance of our cluster of FPGAs implementation has been compared with an HPC implementation. The experimental results have shown an excellent behavior in terms of speed up (up to 脳500) and in terms of solving the scalability problems of this algorithms present in previous works.