Using simulated annealing to design good codes
IEEE Transactions on Information Theory
Parallel island-based genetic algorithm for radio network design
Journal of Parallel and Distributed Computing - Special issue on parallel evolutionary computing
Heuristic algorithms for the terminal assignment problem
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Combinatorial optimization algorithms for radio network planning
Theoretical Computer Science
System Software for Embedded Applications
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Solving the error correcting code problem with parallel hybrid heuristics
Proceedings of the 2004 ACM symposium on Applied computing
The Design Warrior's Guide to FPGAs
The Design Warrior's Guide to FPGAs
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
How to Solve It: Modern Heuristics
How to Solve It: Modern Heuristics
Genetic Algorithms Using Parallelism and FPGAs: The TSP as Case Study
ICPPW '05 Proceedings of the 2005 International Conference on Parallel Processing Workshops
Ianus: An Adaptive FPGA Computer
Computing in Science and Engineering
Advances in Evolutionary Algorithms: Theory, Design and Practice (Studies in Computational Intelligence)
Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword searching
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Searching for Transient Pulses with the ETA Radio Telescope
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA Implementation of Genetic Algorithm for UAV Real-Time Path Planning
Journal of Intelligent and Robotic Systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Computer Organization and Design: The Hardware/Software Interface
Computer Organization and Design: The Hardware/Software Interface
Accelerating Compute-Intensive Applications with GPUs and FPGAs
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Programming Massively Parallel Processors: A Hands-on Approach
Programming Massively Parallel Processors: A Hands-on Approach
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Genetic Algorithm for Boolean minimization in an FPGA cluster
The Journal of Supercomputing
Complete FPGA implemented evolvable image filters
MICAI'06 Proceedings of the 5th Mexican international conference on Artificial Intelligence
A performance evaluation of CUBE: one-dimensional 512 FPGA cluster
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Journal of Systems Architecture: the EUROMICRO Journal
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Many large combinatorial optimization problems tackled with evolutionary algorithms often require very high computational times, usually due to the fitness evaluation. This fact forces programmers to use clusters of computers, a computational solution very useful for running applications of intensive calculus but having a high acquisition price and operation cost, mainly due to the Central Processing Unit (CPU) power consumption and refrigeration devices. A low-cost and high-performance alternative comes from reconfigurable computing, a hardware technology based on Field Programmable Gate Array devices (FPGAs). The main objective of the work presented in this paper is to compare implementations on FPGAs and CPUs of different fitness functions in evolutionary algorithms in order to study the performance of the floating-point arithmetic in FPGAs and CPUs that is often present in the optimization problems tackled by these algorithms. We have taken advantage of the parallelism at chip-level of FPGAs pursuing the acceleration of the fitness functions (and consequently, of the evolutionary algorithms) and showing the parallel scalability to reach low cost, low power and high performance computational solutions based on FPGA. Finally, the recent popularity of GPUs as computational units has moved us to introduce these devices in our performance comparisons. We analyze performance in terms of computation times and economic cost.