Evolving hardware by dynamically reconfiguring xilinx FPGAs

  • Authors:

  • Andres Upegui;Eduardo Sanchez

  • Affiliations:

  • Logic Systems Laboratory – LSL, Ecole Polytechnique Fédérale de Lausanne – EPFL, Lausanne, Switzerland;Logic Systems Laboratory – LSL, Ecole Polytechnique Fédérale de Lausanne – EPFL, Lausanne, Switzerland

  • Venue:
  • ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
  • Year:
  • 2005

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Abstract

Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evolving digital systems by directly mapping a chromosome on the FPGA configuration bitstream. This approach allowed a great degree of flexibility for evolving circuits. Nowadays, FPGAs routing scheme does not allow doing it in such flexible and safe way, so additional constraints must be introduced. In this paper we summarize three techniques for performing hardware evolution by exploiting the capacities of Virtex families. Among our proposals there are high and low level approaches, and coarse and fine grained components. A modular based evolution, with pre-placed and routed components, provides a coarse grain approach. Two techniques for directly modifying LUT contents on hard macros provide a fine grained evolution. Finally, integrating both approaches, coarse and fine grain, provides a more general and powerful framework.