IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Reconfigurable Hardware in Wearable Computing Nodes
ISWC '02 Proceedings of the 6th IEEE International Symposium on Wearable Computers
Developing critical systems with PLD components
Proceedings of the 10th international workshop on Formal methods for industrial critical systems
Evolving hardware by dynamically reconfiguring xilinx FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration
Journal of Real-Time Image Processing
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As the trend in reconfigurable electronics goes towards strong integration, FPGA devices are becoming more and more interesting. They are already used for safety-critical applications such as avionics [9]. Latest FPGA's also enable new techniques such as dynamic partial reconfiguration (DPR), allowing new possibilities in terms of performance and flexibility. Their use in safety-critical systems is considered as impossible nowadays since they must be strictly validated, and DPR brings many new issues. Indeed, the tools used for DPR must be certified, which is barely impossible for the current DPR tools provided by the vendors. We have developed a simple flow upon the usual static one for Xilinx FPGA's that does not require any support of the vendor tools for DPR. This lessens the complexity of tools certification, and make a step towards enabling the certification of DPR for safety-critical applications. Moreover, under strong hypotheses, and by using safe design principles, we show how the complexity of certifying DPR can be reduced.