3D RGB image compression for interactive applications
ACM Transactions on Graphics (TOG)
Wavelets for Computer Graphics: A Primer, Part 1
IEEE Computer Graphics and Applications
Face recognition: A literature survey
ACM Computing Surveys (CSUR)
IEEE Transactions on Pattern Analysis and Machine Intelligence
Local Feature Matching For Face Recognition
CRV '06 Proceedings of the The 3rd Canadian Conference on Computer and Robot Vision
A Modified Non-negative Matrix Factorization Algorithm for Face Recognition
ICPR '06 Proceedings of the 18th International Conference on Pattern Recognition - Volume 03
Enabling certification for dynamic partial reconfiguration using a minimal flow
Proceedings of the conference on Design, automation and test in Europe
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
ACM Transactions on Embedded Computing Systems (TECS)
Efficient architectures for 3D HWT using dynamic partial reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
A novel feature vectors construction approach for face recognition
Transactions on computational science XI
Flexible VLIW processor based on FPGA for efficient embedded real-time image processing
Journal of Real-Time Image Processing
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This paper presents a combination of novel feature vectors construction approach for face recognition using discrete wavelet transform (DWT) and field programmable gate array (FPGA)-based intellectual property (IP) core implementation of transform block in face recognition systems. Initially, four experiments have been conducted including the DWT feature selection and filter choice, features optimisation by coefficient selections and feature threshold. To examine the most suitable method of feature extraction, different wavelet quadrant and scales have been evaluated, and it is followed with an evaluation of different wavelet filter choices and their impact on recognition accuracy. In this study, an approach for face recognition based on coefficient selection for DWT is presented, and the significant of DWT coefficient threshold selection is also analysed. For the hardware implementation, two architectures for two-dimensional (2-D) Haar wavelet transform (HWT) IP core with transpose-based computation and dynamic partial reconfiguration (DPR) have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are also discussed in this paper.