Efficient architectures for 3D HWT using dynamic partial reconfiguration

  • Authors:

  • A. Ahmad;B. Krill;A. Amira;H. Rabah

  • Affiliations:

  • Department of Electronic and Computer Engineering, School of Engineering and Design, Brunel University, West London, UB83PH Uxbridge, United Kingdom and Department of Computer Engineering, Faculty ...;Department of Electronic and Computer Engineering, School of Engineering and Design, Brunel University, West London, UB83PH Uxbridge, United Kingdom;Nanotechnology and Integrated BioEngineering Centre (NIBEC), University of Ulster, Shore Road Newtownabbey, BT37 0QB Belfast, Northern Ireland;Laboratoire d'Instrumentation, Electronique de Nancy, University Henri Poincare, 540003 Nancy, France

  • Venue:
  • Journal of Systems Architecture: the EUROMICRO Journal
  • Year:
  • 2010

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Abstract

This paper presents the design and implementation of three dimensional (3D) Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR) mechanism on field programmable gate array (FPGA). Due to the separability property of the multi-dimensional HWT, the proposed architecture has been implemented using a cascade of three N-point one dimensional (1D) HWT and two transpose memories for a 3D volume of NxNxN suitable for real-time 3D medical imaging applications. These applications require continuous hardware servicing, hence DPR has been introduced. Two architectures were synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are analysed in this paper.