A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
The Vision of Autonomic Computing
Computer
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
RMB -- A Reconfigurable Multiple Bus Network
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Dynamic Reconfiguration: Architectures and Algorithms (Series in Computer Science (Kluwer Academic/Plenum Publishers).)
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Digital Image Processing (3rd Edition)
Digital Image Processing (3rd Edition)
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Networked, Lightweight and Partially Reconfigurable Platform
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Operating System Support for Difference-Based Partial Hardware Reconfiguration
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable Multithreading Architectures: A Survey
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Efficient architectures for 3D HWT using dynamic partial reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Cross-architectural design space exploration tool for reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
A self-reconfigurable FPGA-based platform for prototyping future pervasive systems
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Journal of Signal Processing Systems
The Journal of Supercomputing
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A low overhead abstract architecture for FPGA resource management
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
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Computer architects have been studying the dynamically reconfigurable computer (Schaumont, Verbauwhede, Keutzer, and Sarrafzadeh, "A Quick Safari through the Reconfiguration Jungle," in Proc. of the 38th Design Automation Conference, Las Vegas, pp. 127---177, 2001) for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic (Kephart and Chess, Computer, 36:41---52, 2003; IBM Autonomic Computing Initiative, (http://www.research.ibm.com/autonomic/)) and organic computing (Müller-Schloer, von der Malsburg, and Würtz, Inform.-Spektrum, 27:332---336, 2004; The Organic Computing Page, (http://www.organic-computing.org)). Much research work is currently devoted to models for partial hardware module relocation (SPP1148 Reconfigurable Computing Priority Program, (http://www12.informatik.uni-erlangen.de/spprr/)) and dynamically reconfigurable hardware reconfiguration on e.g., FPGA-based platforms. However, there are many physical restrictions and technical problems limiting the scope or applicability of these approaches. This led us to the development of a new FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from (a) a new slot-oriented hardware architecture, (b) a set of novel inter-module communication paradigms, and (c) concepts for dynamic and partial reconfiguration management.