ACM Transactions on Computer Systems (TOCS)
Run-time compaction of FPGA designs
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Mapping a domain specific language to a platform FPGA
Proceedings of the 41st annual Design Automation Conference
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Heterogeneous Floorplanning for FPGAs
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Standards: The P1685 IP-XACT IP Metadata Standard
IEEE Design & Test
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Journal of VLSI Signal Processing Systems
OpenFPGA CoreLib core library interoperability effort
Parallel Computing
Industrial IP integration flows based on IP-XACT™ standards
Proceedings of the conference on Design, automation and test in Europe
Automatic bus macro placement for partially reconfigurable FPGA designs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enhancing the Productivity of Radio Designers with RapidRadio
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
400 Gb/s Programmable Packet Parsing on a Single FPGA
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
Floorplan Design for Multimillion Gate FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning for Partially Reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The latest FPGA devices provide the headroom to implement large-scale and complex systems. A key requirement is the integration of modules from diverse sources to promote modular design and reuse. A contrary factor is that using dynamic partial reconfiguration typically requires low-level planning of the system implementation. In this article, we introduce ReShape: a high-level approach for designing reconfigurable systems by interconnecting modules, which gives a “plug and play” look and feel, is supported by tools that carry out implementation functions, and is carried through to support system reconfiguration during operation. The emphasis is on the inter-module connections and abstracting the communication patterns that are typical between modules: for example, the streaming of data, or the reading and writing of data to and from memory modules. The details of wiring and signaling are hidden from view, via metadata associated with individual modules. This setting allows system reconfiguration at the module level, both by supporting type checking of replacement modules and by managing the overall system implementation, via metadata associated with its FPGA floorplan. The methodology and tools have been implemented in a prototype targeted to a domain-specific setting---high-speed networking---and have been validated on real telecommunications design projects.