OpenFPGA CoreLib core library interoperability effort

Authors:
M. Wirthlin;D. Poznanovic;P. Sundararajan;A. Coppola;D. Pellerin;W. Najjar;R. Bruce;M. Babst;O. Pritchard;P. Palazzari;G. Kuzmanov
Affiliations:
Brigham Young University, 448 CB, Provo, Utah, 84602, USA;SRC Computers, Inc., 4240 N. Nevada Avenue, Colorado Springs, CO 80907, USA;Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124, USA;OptNgn Software, LL, 2828 Corbett Avenue, Portland, OR 97201, USA;Impulse Accelerated Technologies, 550 Kirkland Way, Suite 408, Kirkland, Washington 98033-6240, USA;Department of Computer Science & Engineering, University of California Riverside, Riverside, CA 92521, USA;Nallatech, Boolean House, One Napier Park, Glasgow G68 0BH, UK and Institute for System Level Integration, The Alba Centre, Livingston, Scotland EH54 7EG, UK;DSPlogic, Inc., 13017 Wisteria Drive, #420, Germantown, MD 20874, USA;Altera Corporation, 110 Cooper St, Suite 201, Santa Cruz, CA 95062, USA;Ylichron Srl, c/o C.R. ENEA Casaccia, Via Anguillarese, 301, 00123 S. Maria di Galeria, Rome, Italy;Computer Engineering, EEMCS, TU Delft, Mekelweg 4, 2628 CD, Delft, The Netherlands
Venue:
Parallel Computing
Year:
2008

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Abstract

This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented.