Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs

Authors:
Xiaojun Wang;Brent E. Nelson
Affiliations:
-;-
Venue:
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2003

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Abstract

Low latency, high throughput and small area arethree major design considerations of an FPGA design.In this paper, we present a high radix SRT divisionalgorithm and a binary restoring square root algorithm.We describe three implementations of floating-pointdivision operations with variable width and precisionbased on Virtex-2 FPGAs.One is a low costiterative implementation; another is a low latency arrayimplementation; and the third is a high throughputpipelined implementation.The implementationsof floating-point square root operations are presentedas well.In addition to presenting the design of thesemodules, we analyze the tradeoffs among cost, latencyand throughput with strategies on how to reduce thecost, or improve the performance.