Digital communications: fundamentals and applications
Digital communications: fundamentals and applications
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
High-precision division and square root
ACM Transactions on Mathematical Software (TOMS)
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Wireless Communications: Principles and Practice
Wireless Communications: Principles and Practice
A New Non-Restoring Square Root Algorithm and its VLSI Implementation
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Cost/Performance Tradeoff of n-Select Square Root Implementations
ACAC '00 Proceedings of the 5th Australasian Computer Architecture Conference
Implementation of single precision floating point square root on FPGAs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Parallel-array implementations of a non-restoring square root algorithm
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Pipelining of double precision floating point division and square root operations
Proceedings of the 44th annual Southeast regional conference
Modular array structure for non-restoring square root circuit
Journal of Systems Architecture: the EUROMICRO Journal
Floating-point division and square root using a Taylor-series expansion algorithm
Microelectronics Journal
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The square root is a basic arithmetic operation in image and signal processing. We present a novel pipelined architecture to implement N-bit fixed-point square root operation on an FPGA using a non-restoring pipelined algorithm that does not require floating-point hardware. Pipelining hazards in its hardware realization are avoided by modifying the classic non-restoring algorithm, thus resulting in a 13% improved latency. Furthermore, the proposed architecture is flexible allowing modification as per individual application needs. It is demonstrated that the proposed architecture is approximately four times faster than its popular counterparts and at the same time it consumes 50% less energy for envelope detection at 268 MHz sampling rate.