Cost/Performance Tradeoff of n-Select Square Root Implementations

Authors:
Wanming Chu;Yamin Li
Affiliations:
-;-
Venue:
ACAC '00 Proceedings of the 5th Australasian Computer Architecture Conference
Year:
2000

Citing 0
Cited 2

Modular array structure for non-restoring square root circuit

Journal of Systems Architecture: the EUROMICRO Journal
Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm

Journal of Signal Processing Systems

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Abstract

Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fully-pipelined n-select implementations (nS-Root) based on a non-restoring-remainder square root algorithm. The nS-Root uses a parallel array of carry-save adders (CSAs). For a square root bit calculation, a CSA is used once. This means that the calculations can be fully pipelined. It also uses the n-way root-select technique to speedup the square root calculation. The cost/performance evaluation shows that n=2 or n=2.5 is a suitable solution for designing a high-speed fully pipelined square root unit while keeping the low-cost.