Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
A New Non-Restoring Square Root Algorithm and its VLSI Implementation
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Cost/Performance Tradeoff of n-Select Square Root Implementations
ACAC '00 Proceedings of the 5th Australasian Computer Architecture Conference
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Parallel-array implementations of a non-restoring square root algorithm
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Digit Selection for SRT Division and Square Root
IEEE Transactions on Computers
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication
Journal of VLSI Signal Processing Systems
Pipelining of double precision floating point division and square root operations
Proceedings of the 44th annual Southeast regional conference
A Decimal Floating-Point Divider Using Newton---Raphson Iteration
Journal of VLSI Signal Processing Systems
Journal of Signal Processing Systems
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Square root is an operation performed by the hardware in recent generations of processors. The hardware implementation of the square root operation is achieved by different means. One of the popular methods is the non-restoring algorithm. In this paper, the classical non-restoring array structure is improved in order to simplify the circuit. This reduction is done by eliminating a number of circuit elements without any loss in the precision of the square root or the remainder. For a 64-bit non-restoring circuit the area of the suggested circuit is about 44% smaller than that of a conventional non-restoring array circuit. Furthermore, in order to create an environment for modular design of the non-restoring square root circuit, a number of modules are suggested. Using these modules it is possible to construct any square root circuit with an arbitrary number of input bits. The suggested methodology results in an expandable design with reduced-area. Analytical and simulation results show that the delay of the proposed circuit, for a 64-bit radicand, is 80% less than that of a conventional non-restoring array circuit.