On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Radix-4 Square Rot Without Initial PLA
IEEE Transactions on Computers
IEEE Transactions on Computers
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
Journal of VLSI Signal Processing Systems
Choices of Operand Truncation in the SRT Division Algorithm
IEEE Transactions on Computers
It Takes Six Ones To Reach a Flaw
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Revisiting SRT Quotient Digit Selection
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
SRT division diagrams and their usage in designing intergrated circuits for division
SRT division diagrams and their usage in designing intergrated circuits for division
Minimizing the complexity of SRT tables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leading Guard Digits in Finite Precision Redundant Representations
IEEE Transactions on Computers
A pipelined divider with a small lookup table
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Modular array structure for non-restoring square root circuit
Journal of Systems Architecture: the EUROMICRO Journal
Design issues and implementations for floating-point divide-add fused
IEEE Transactions on Circuits and Systems II: Express Briefs
Decimal Division Algorithms: The Issue of Partial Remainders
Journal of Signal Processing Systems
Hi-index | 14.98 |
The quotient digit selection in the SRT division algorithm is based on a few most significant bits of the remainder and divisor, where the remainder is usually represented in a redundant representation. The number of leading bits needed depends on the quotient radix and digit set, and is usually found by an extensive search, to assure that the next quotient digit can be chosen as valid for all points (remainder, divisor) in a set defined by the truncated remainder and divisor, i.e., an "uncertainty rectangle.驴 This paper presents expressions for the number of bits needed from the truncated remainder and divisor (the truncation parameters), thus eliminating the need for a search through the truncation parameter space for validation. The analysis is then extended to the digit selection in SRT square root algorithms, where it is shown that, in general, it may be necessary to increase the number of leading bits needed for digit determination in a combined divide and square root algorithm. An easy condition to check the number of bits needed is established, also checking the number of initial digits of the root may have to be found by other means, e.g., by table look-up. The minimally redundant, radix-4 combined divide and square root algorithm is finally analyzed and it is shown that, in this case, it can be implemented without such a special table to determine initial digits for the square root.