On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Radix-16 Signed-Digit Division
IEEE Transactions on Computers
Higher Radix Square Root with Prescaling
IEEE Transactions on Computers - Special issue on computer arithmetic
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Simple Radix-4 Division with Operands Scaling
IEEE Transactions on Computers
A Fast Division Algorithm for VLSI
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
SRT division diagrams and their usage in designing intergrated circuits for division
SRT division diagrams and their usage in designing intergrated circuits for division
Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
Digit Selection for SRT Division and Square Root
IEEE Transactions on Computers
A novel implementation of radix-4 floating-point division/square-root using comparison multiples
Computers and Electrical Engineering
Minimizing the complexity of SRT tables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an analysis of the number of partial remainder digits and divisor bits that must be examined in the SRT division algorithm. The number of examined digits is found to be the same for both signed-digit and 2s-complement partial remainder representations, and appears to increase as 3log2r approximately, where r is the radix of the divider. In some cases, it proves advantageous to examine a fractional number of remainder digits by inspecting more positive than negative bits.