A novel implementation of radix-4 floating-point division/square-root using comparison multiples

Authors:
H. Nikmehr;B. Phillips;C. C. Lim
Affiliations:
Department of Computer Engineering, Bu-Ali Sina University, Hamedan, Iran;School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, SA 5005, Australia;School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, SA 5005, Australia
Venue:
Computers and Electrical Engineering
Year:
2010

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Abstract

A new implementation for minimally redundant radix-4 floating-point SRT div/sqrt (division/square-root) with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the magnitude of the quotient (root) digit is calculated by comparing the truncated partial remainder with 2 limited precision multiples of the divisor (partial root). The digit sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using the logical synthesis (Synopsys DC with Artisan 0.18@mm typical library) shows a latency of 2.5ns for the recurrence of the proposed div/sqrt. This is less than of the conventional implementation.