Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
Fast decimal floating-point division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel implementation of radix-4 floating-point division/square-root using comparison multiples
Computers and Electrical Engineering
| Hi-index | 0.00 |
The increasing computation requirements of modern computer applications have stimulated a large interest in developing extremely high-performance floating- point dividers. A variety of division algorithms are available, with SRT being utilized in many computer systems.A careful analysis of SRT divider topologies has demonstrated that a relatively simple divider designed in anaggressive circuit style can achieve extremely high performance. Further, an aggressive circuit implementation can minimize many of the performance advantages of more complex divider algorithms. This paper presents the tradeoffs of the different divider topologies, the design of the divider, and performance results.