High-performance carry chains for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Using partitioning to help convergence in the standard-cell design automation methodology
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect scaling implications for CAD
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the relevance of wire load models
Proceedings of the 2001 international workshop on System-level interconnect prediction
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
The future of logic synthesis and verification
Logic Synthesis and Verification
Performance Comparison of VLSI Adders Using Logical Effort
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Structure Independent Representation of Output Transition Time for CMOS Library
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Design and synthesis of dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A Counterflow Pipeline Experiment
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Energy and Performance Models for Clocked and Asynchronous Communication
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Congestion and Starvation Detection in Ripple FIFOs
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay-Optimized Implementation of IEEE Floating-Point Addition
IEEE Transactions on Computers
A reconfigurable unit for a clustered programmable-reconfigurable processor
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Fast Comparisons of Circuit Implementations
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Expert System Perimeter Block Placement Floorplanning
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Mixed-clock issue queue design for energy aware, high-performance cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Practical methodology of post-layout gate sizing for 15% more power saving
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Time Budgeting in a Wireplanning Context
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
Critical evaluation of SOI design guidelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Oriented CMOS Circuit Optimization Protocol
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
New Models of Prefix Adder Topologies
Journal of VLSI Signal Processing Systems
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Optimization objectives and models of variation for statistical gate sizing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Design of a cell library for asynchronous microengines
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Efficient and accurate gate sizing with piecewise convex delay models
Proceedings of the 42nd annual Design Automation Conference
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Digit-Recurrence Dividers with Reduced Logical Depth
IEEE Transactions on Computers
Architectural Considerations for Energy Efficiency
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A flexibility aware budgeting for hierarchical flow timing closure
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Energy optimization of pipelined digital systems using circuit sizing and supply scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Low-power fanout optimization using MTCMOS and multi-Vt techniques
Proceedings of the 2006 international symposium on Low power electronics and design
Modeling and estimating leakage current in series-parallel CMOS networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
DAG based library-free technology mapping
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Digital Circuit Optimization via Geometric Programming
Operations Research
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Techniques for effective distributed physical synthesis
Proceedings of the 44th annual Design Automation Conference
A comparative study of CMOS gates with minimum transistor stacks
Proceedings of the 20th annual conference on Integrated circuits and systems design
A New Cost-Effective Technique for QoS Support in Clusters
IEEE Transactions on Parallel and Distributed Systems
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Area and delay trade-offs in the circuit and architecture design of FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Timing optimization in logic with interconnect
Proceedings of the 2008 international workshop on System level interconnect prediction
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Stack sizing for optimal current drivability in subthreshold in circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic gates as repeaters (LGR) for area-efficient timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power circuit design based on heterojunction tunneling transistors (HETTs)
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Best of both worlds: A bus enhanced NoC (BENoC)
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
Characterizing asynchronous variable latencies through probability distribution functions
Microprocessors & Microsystems
Designing high-speed adders in power-constrained environments
IEEE Transactions on Circuits and Systems II: Express Briefs
Delay estimation and sizing of CMOS logic using logical effort with slope correction
IEEE Transactions on Circuits and Systems II: Express Briefs
Low-power fanout optimization using multi threshold voltages and multi channel lengths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
High-level synthesis algorithm for the design of reconfigurable constant multiplier
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of a High-Throughput Distributed Shared-Buffer NoC Router
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A novel implementation of radix-4 floating-point division/square-root using comparison multiples
Computers and Electrical Engineering
Design and evaluation of decimal array multipliers
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An efficient delay model for MOS current-mode logic automated design and optimization
IEEE Transactions on Circuits and Systems Part I: Regular Papers
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel dual-Vth independent-gate FinFET circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
C-pack: a high-performance microprocessor cache compression algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Fast comparisons of circuit implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparison of high-performance VLSI adders in the energy-delay space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Finding the energy efficient curve: gate sizing for minimum power under delay constraints
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Energy and performance models for synchronous and asynchronous communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A quick method for energy optimized gate sizing of digital circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
On the complexity of min-max sorting networks
Information Sciences: an International Journal
Closed-Form bounds for interconnect-aware minimum-delay gate sizing
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Speed indicators for circuit optimization
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Delay constrained register transfer level dynamic power estimation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Methodology for energy-efficient digital circuit sizing: important issues and design limitations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Circuit sizing and supply-voltage selection for low-power digital circuit design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A clock generator driven by a Unified-CBiCMOS buffer driver for high speed and low energy operation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Timing verification of gasp asynchronous circuits: predicted delay variations observed by experiment
Concurrency, Compositionality, and Correctness
Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection
Proceedings of the fifth ACM conference on Security and Privacy in Wireless and Mobile Networks
From energy-delay metrics to constraints on the design of digital circuits
International Journal of Circuit Theory and Applications
Subthreshold leakage modeling and estimation of general CMOS complex gates
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Mixed FBB/RBB: a novel low-leakage technique for FinFET forced stacks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable high-radix router microarchitecture using a network switch organization
ACM Transactions on Architecture and Code Optimization (TACO)
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing
Microprocessors & Microsystems
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the International Conference on Computer-Aided Design
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
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