On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
High Speed Redundant Adder and Divider in Output Prediction Logic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
Designing high-speed adders in power-constrained environments
IEEE Transactions on Circuits and Systems II: Express Briefs
Computer Arithmetic: Algorithms and Hardware Designs
Computer Arithmetic: Algorithms and Hardware Designs
High-Radix Multiplier-Dividers: Theory, Design, and Hardware
IEEE Transactions on Computers
A new optimized high-speed low-power data-driven dynamic (d3l) 32-bit kogge-stone adder
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of SPD^3L family structure (SPCD^3L: Split-Path Clock-Data driven Dynamic Logic) is presented. Through the modification, the clock signal is also used to pre-charge some critical parts of the circuit. Performance of the circuit is evaluated at different simulation corners. The results show that, compared with Domino structure, the proposed circuit has lower power consumption and higher speed. Latency of the divider is equal to 10 half clock cycles. The design is simulated using HSPICE in a 1.8-V TSMC_180nm CMOS process.