An optimal low-power/high performance DDP-based Cobra-H64 cipher
Proceedings of the 3rd international conference on Mobile multimedia communications
Accelerating seismic computations using customized number representations on FPGAs
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
An RNS implementation of an Fpelliptic curve point multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A low-complexity high-radix RNS multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Real-time FPGA architecture of modified stable Euler-number algorithm for image binarization
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Formalization of a parameterized parallel adder within the coq theorem prover
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-speed FPGA 10's complement adders-subtractors
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Concurrent calculations on reconfigurable logic devices applied to the analysis of video images
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
System on chip coprocessors for high speed image feature detection and matching
ACIVS'11 Proceedings of the 13th international conference on Advanced concepts for intelligent vision systems
Journal of Signal Processing Systems
Biometric encryption based on a fuzzy vault scheme with a fast chaff generation algorithm
Future Generation Computer Systems
Modified stable Euler-number algorithm implementation for real-time image binarization
Journal of Real-Time Image Processing
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