Image difference threshold strategies and shadow detection
BMVC '95 Proceedings of the 1995 British conference on Machine vision (Vol. 1)
Thresholding for Change Detection
ICCV '98 Proceedings of the Sixth International Conference on Computer Vision
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Embedded active vision system based on an FPGA architecture
EURASIP Journal on Embedded Systems
A new binarization algorithm based on maximum gradient of histogram
ICIG '07 Proceedings of the Fourth International Conference on Image and Graphics
Local Properties of Binary Images in Two Dimensions
IEEE Transactions on Computers
Image change detection algorithms: a systematic survey
IEEE Transactions on Image Processing
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The Stable Euler-Number based image binarization gives excellent visual results for video frames containing high amount of image noise. Being computationally expensive, its implementations are limited to general purpose processors for the most cost-effective solution or in application specific integrated circuits for maximum performance. This paper proposes a modified Stable Euler-Number based algorithm for image binarization and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture. The end result is a design that out-performs known software implementations while keeping the amount of noisy pixels introduced during the binarization process to a minimum. The hardware implementation results show that the proposed architecture gives accurate results compared to the software implementation.