MPEG Video Compression Standard
MPEG Video Compression Standard
An Applications Approach to Evolvable Hardware
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
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This paper presents the design and implementation on FPGA devices of an algorithm for computing similarities between neighboring frames in a video sequence using luminance information. By taking advantage of the well-known flexibility of Reconfigurable Logic Devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexing. The experimental results show the tradeoff between concurrent sequential resources and the functional blocks needed to achieve maximum operational speed while achieving minimum silicon area usage. To evaluate system efficiency, we compare the performance of the hardware solution to that of calculations done via software using general-purpose processors with and without an SIMD instruction set.