Computer Approximations
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IEEE Transactions on Computers
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IEEE Transactions on Computers
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IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems
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ISCSCT '08 Proceedings of the 2008 International Symposium on Computer Science and Computational Technology - Volume 01
A Novel Time and Energy Efficient Cubing Circuit Using Vedic Mathematics for Finite Field Arithmetic
ARTCOM '09 Proceedings of the 2009 International Conference on Advances in Recent Technologies in Communication and Computing
Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier
ACT '09 Proceedings of the 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies
A new VLSI architecture of parallel multiplier-accumulator based on radix-2 modified booth algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of high speed vedic multiplier for decimal number system
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like 'Urdhva-tiryakbyham' (UT) and 'Nikhilam Navatascaramam Dasatah' (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only ~42.13ns while the power consumption of the same was ~58.82mW for a layout area of ~6mm^2. Improvement in speed was found to be ~33% and ~24% while corresponding reduction of power consumption in ~34.48% and ~24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.